The Eve of Transformation in Automotive Microchips

As the automotive industry is at the cusp of significant transformation, there is a growing need for advanced electronic and electrical architectures that suit the demands of modern vehiclesCentral to this evolution is the emergence of centralized computing units, which are crafted to handle an increasing array of functionalitiesThe advent of fusion chips and chiplet-based designs represents a pivotal shift in this direction, driving the next generation of Software-Defined Vehicles (SDVs) towards more sophisticated systems.

Market analysis indicates a rapid move towards centralized electric/electronic (E/E) architectures, with a forecast that by 2032, approximately 30% of all vehicles will incorporate E/E frameworks featuring regional controllersSuch a shift demands high-performance computing units that can process vast amounts of data with speed and accuracyIn fact, it is anticipated that within the next decade, the market for automotive microelectronics and logic semiconductors will soar from its current valuation of around $60 billion to over $140 billion, outpacing other sectors within the semiconductor landscape with an impressive CAGR of 10%.

High-performance computing units will play a pivotal role in enabling not only advanced driving assistance systems (ADAS) but also the capabilities required for full autonomy in driving (AD). These computing units are designed to support various functions, including infotainment and vehicle dynamicsThe industry sees two primary prototypes emerging: dedicated, domain-specific computing units and overarching centralized processing units that manage multiple domainsThis dual approach allows Original Equipment Manufacturers (OEMs) and tier-one suppliers to implement centralized computing using a variety of methods—be it rack-based setups, multi-chip printed circuit boards (PCBs), or through fusion chips that consolidate multiple functionalities on a single chip.

The selection process for the most efficient Systems-on-a-Chip (SoCs) or System-in-Package (SiP) configurations is critical for several reasons

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First, the computation required for autonomous driving—which entails perceiving and identifying other vehicles and road users—is heavily reliant on proper SoC architectureAdditionally, these chips facilitate cutting-edge infotainment services and contribute to generative AI applications, such as in-car assistantsSecond, these components are significant cost drivers, directly influencing the Bill of Materials (BOM). Finally, their power consumption profiles are crucial for ensuring the fuel efficiency of vehicles, especially in the shift towards Battery Electric Vehicles (BEVs).

In light of these findings, it is evident that automotive OEMs are making substantial investments to enhance computing capabilities and efficienciesTwo emergent trends gaining traction in the concept phase of upcoming E/E architectures are the adoption of fusion chips and chiplet-based designsThis article delves into these technologies, shedding light on their roles as driving forces for centralized computing in future automotive developments and addressing why they are crucial considerations for Chief Technology Officers (CTOs) in shaping centralized computing strategies.

Fusion chips can be viewed as a logical next step towards enhanced functionalities and integration in SDVsThese chips combine infotainment and ADAS/AD capabilities into a singular unit, offering the promise of improved efficiency and reduced overall system complexityThis streamlining is particularly advantageous as both domains require advanced multicore central processing units (CPUs), graphics processing units (GPUs), AI accelerators, and digital signal processors, all achieved at finely-tuned node sizes (sub-10nm to maximize processing power and efficiency).

However, discrepancies between the two segments must be recognizedWhile infotainment applications may warrant some functional safety considerations (e.g., for cockpit clusters), the ADAS/AD realm requires stringent compliance with Automotive Safety Integrity Level B (ASIL-B) and ASIL-D standards

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These levels of safety are imperative because ADAS/AD operations often involve real-time critical functions, such as actuator control, where failures could have dire consequencesConsequently, the exclusive use of safety island configurations, which are frequently employed in infotainment systems, is inadequate for ADAS/AD functionalities.

Furthermore, tightly designed hardware/software (HW/SW) collaborations are essential in the ADAS/AD sector to optimize computing hardware for the specific neuromorphic architectures required by perception algorithmsOver recent years, while challenges remain in fusion chip design, several fabless semiconductor companies and newcomers have begun to realize this theoretical framework into practical applicationsA number of tier-one suppliers have showcased designs employing fusion chips, heralding their advantages within the SDV context.

Utilizing fusion chips allows OEMs to reduce the overall physical computing units required, thereby simplifying the integration and consolidation of computing logicThis approach is particularly critical for facilitating over-the-air (OTA) updates — a fundamental driver for SDVsIn the long term, the use of fusion chips can significantly streamline the toolchain and development frameworks in the realms of infotainment and ADAS/AD, resulting in anticipated cost savings.

Yet, transitioning to fusion chips does not come without challengesThe increased technological complexity necessitates robust verification processes to ensure independence from interference, as computing capabilities for infotainment and ADAS/AD must not compromise each otherAdditionally, the collaborative demands between the two domains require enhanced organizational oversight.

Another challenge lies in meeting redundancy requirements stipulated for level three (L3) and above autonomous driving systems, which necessitate conditional automation, computational redundancy, and reliable actuation (for braking and steering). When combining infotainment and ADAS/AD capabilities into a single, highly-integrated chip, the absence of a secondary chip becomes conceivable

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However, this could lead to overhead incurred by failing to allocate sufficient computational power when the primary chip encounters issues.

Electromagnetic compatibility (EMC) requirements become more intricate, reflecting a need to balance functional safety demands alongside unique acceleratorsAdditionally, there is a growing concern about the potential loss of the freedom to choose the optimal vendor for each domain, leading to potential lock-in effects.

Responses from industry surveys reveal that the top three challenges facing the adoption of fusion SoCs are ensuring interference freedom, dealing with organizational complexities, and adhering to redundancy requirements set forth for ADAS/AD, with issues of scalability and manufacturing difficulties considered relatively minor.

Examining the requirements for higher levels of automated driving, the appeal of fusion chips particularly stands out for applications targeting L0 to L2 scenarios, such as Adaptive Cruise Control (ACC), Lane Departure Warning (LDW), and Automatic Emergency Braking (AEB) due to their lower complexity compared to L3 and above scenariosNotably, areas like driver and occupant monitoring are gaining importance in light of emerging regulations from the upcoming New Car Assessment Program (NCAP) in Europe.

On the infotainment side, fusion chips are ideally suited to manage a broad spectrum of functionalities, including control of cockpit displays, central stack systems, passenger displays, augmented reality (AR) interfaces, surround-view parking assist, rear-seat entertainment, and electronic rear-view mirrors.

Recent announcements regarding the fusion chips indicate that they are projected to debut between 2026 and 2027, with primary adopters likely to include cost-conscious mass OEMs and innovators open to advanced technological developments.

Shifting the focus to chiplet technology, this concept represents an advanced packaging form aimed at enhancing the performance, functionality, and integration of semiconductor devices

The chiplet architecture signifies a paradigm shift in semiconductor design, facilitating modular integration of multiple specialized chips within a single packageIt allows OEMs to select optimal technology solutions for each subcomponent, underscoring that not every component must be produced at cutting-edge node sizesHence, chiplet designs can be employed in both dedicated ADAS/AD and infotainment chips as well as fusion chips.

The implementation of flexibility enables considerations for overall chip designs that may support varying computational loadsRegional controllers emerge as a compelling application area given that their computational needs vary based on prototypes—ranging from simple I/O aggregation units to matured computing units.

Modern chips have not all been integrated onto a singular silicon die; rather, various components of the chiplet must utilize the most suitable and economically viable technology node sizes independentlyThis means that CPU and accelerator subsystems may adopt the smallest available node sizes, while other features could function at more extensive node sizesTo ensure that independently produced components function seamlessly together, a universal interface standard, such as Universal Chiplet Interconnect Express (UCIe), is paramountNumerous efforts are underway to establish these standards.

In the automotive domain, experts highlight two significant advantages of chiplet-based designs: a reduction in overall chip dimensions and the Lego principle of design modularityThe utilization of chiplets mitigates the increase in chip size that single-chip designs often provokeIn the past five years, as the size of intricate chips has nearly reached extreme ultraviolet lithography mask limits (i.e., 858 square millimeters), larger chips—particularly GPUs in data centers—are increasingly vulnerable to defects due to greater surface area, subsequently impacting yield rates adversely.

In contrast, the principle of Lego modularity allows automotive OEMs to mix and match components from an existing design pool to meet specific requirements

The added benefits of component reusability become evident, especially considering the automotive industry’s lower production scales compared to other sectors (e.g., nearly 100 million cars produced annually versus smartphone shipments nearing 1.5 billion units). Emphasizing reusable components fosters cost-efficiency in target chip designs while enhancing scalability and reducing time-to-market for new chips through selective sourcing of necessary components.

Surveys indicate that a significant proportion of stakeholders within the automotive semiconductor value chain (61%) appreciate the design flexibility afforded by mixing and matching components, identifying it as the primary motivation behind adopting chiplet technologyWhile lowering operating costs and increasing individual intellectual property (IP) component yields are also valued advantages, they hold comparatively less weight at 19%.

Equally, the ecosystem is paramount to the success of chiplet technology, fostering standardization and creating environments encouraging chiplet adoption across various verticals including data centers and automotive applicationsThe UCIe standard represents one of the most significant advancements in these standardization effortsSince the inaugural standard was published in March 2022, an automotive working group has been established to contribute to revisions tailored for vehicle applications.

Beyond standardization, emerging ecosystems also play a critical role in promoting adoptionFor instance, the Automotive Chiplet Alliance sponsored by imec, which brings together over 50 participants from the automotive semiconductor value chain, aims to discuss and exchange insights relating to automotive chiplet design advancements.

However, the chiplet technology remains nascent, demanding OEMs to consider the challenges associated with implementing chiplets, especially as they pertain to series deploymentsAutomotive readiness criteria require that chip designs satisfy all necessary devices and manufacturing specifications (e.g., AEC-Q100 and IATF 16949) and endure harsh environmental conditions such as vibrations and temperature extremes

Data center use-cases currently offer more stable environments with fewer threats compared to automotive applications.

The need for interconnect standardization must also be emphasized, as stated previouslyEcosystem participants should focus on developing a unified standard that permits combinatorial design architecturesPresently, major players within the industry are forming various alliances and standards organizationsIt is crucial to establish a globally-accepted standard that brings the Lego principle to fruition.

Adoption of new development paradigms and operational openness is equally vitalStakeholders within the value chain (IP designers, foundries, integrators, and package manufacturers) might seek novel collaboration frameworks to facilitate widespread chiplet adoptionWhile this is viewed as a critical element by all parties, timely implementation remains a challenge, partly due to the hurdles surrounding intellectual property and responsibilities, such as identifying who will oversee the overall reliability of chips built with modular componentsFrom a validation and verification perspective, utilizing a mixing 'shop' approach remains unrealistic to many stakeholders.

Most industry leaders within the value chain foresee a broader adoption of chiplets within the next decadeSurveys reveal that 48% of industry leaders expect automotive chiplets to emerge between 2027 and 2030, while 38% project a timeframe extending from 2030 to 2035. Notably, only 8% anticipate a faster rollout, looking to 2025-2027. This gradual timeline aligns with the automotive industry's typical growth and development cycles.

Furthermore, this transition is expected to unfold incrementallyWhile the Lego principle offers promising prospects, initial chip designs will likely follow a homogenous pathKnowledge modules are anticipated to derive from the same supplier and utilize proprietary or established standards, like Peripheral Component Interconnect Express (PCIe). Subsequently, designs considering components from external sources may emerge, addressing liability concerns and establishing a foundation for genuine heterogeneous designs combining multiple vendors or technology node sizes, an outcome most likely to manifest in the mid-2030s and beyond.

The significance of chiplet-based designs is evident, as they empower chip manufacturers to tiptoe around existing boundaries when demands for computing escalate, all while pursuing cost-efficiencies

Upon establishing a robust chip ecosystem and accompanying standards, stakeholders can start quantifying the benefits and opportunities arising from prevailing applications.

The rise of SDVs and the challenges within the supply chain are driving automotive OEMs to dig deeper into the semiconductor value chainOEMs acknowledge the imperative of understanding semiconductor technology comprehensively to retain competitive advantages in the realms of autonomous driving and infotainment functionalities.

This trend impacts all participants within the automotive semiconductor landscape, particularly OEMs, tier-one suppliers, integrated device manufacturers (IDMs), and fabless entitiesThe essential decisions surrounding fusion chip adoption must likely be made within the next two to four years, while addressing chiplet concerns may be determined further down the line.

The automotive computing unit market is poised for growth, anticipated to surge from $96 billion in 2023 to $148 billion by 2030, with a compound annual growth rate (CAGR) of approximately 6%. This reflects a significant shift, driven by the centralization and integration trends emerging within the industry.

Specifically, the growth in body and chassis computing units is expected to be limited, registering a mere annual growth rate of 1% to 2% while powertrain units may even experience slight declinesThis downturn indicates that while the functionalities represented by these units transition to regional controllers or centralized computing units (such as vehicle dynamics computing units), consequently, these components may also face a shrinking scope of operational demands.

Conversely, significant growth rates are observed in the ADAS/AD and infotainment categories, exhibiting CAGRs of 22% and 6%, respectivelyThis surge is propelled by an increasing number of vehicles equipped with L2+ functionalities, including hands-free and eyes-off driving.

According to McKinsey analysis, the market value for regional controllers is projected to reach $3 billion by 2030, while centralized computing units (such as fusion SoCs and vehicle dynamics computing units) will see their market value reach $8 billion.

In navigating the adoption of fusion SoCs, OEMs are urged to consider strategic areas of significance

For instance, evaluating if there exists sufficient software expertise and control over the software architectures relevant to the fusion SoCs’ integrated demands is criticalMoreover, deciding what levels of autonomy and what intended functionalities will be supported are paramountGovernance structures for ADAS/AD and infotainment teams, along with facilitation of development timelines, also play a crucial role.

OEMs must also weigh procurement strategies that may influence decisions regarding selecting suppliers for ADAS/AD and infotainment chips, all while considering potential impacts on supply chain resilienceAdditionally, they should assess the economic implications from a BOM and total cost of ownership perspectiveQuestions such as potential cost savings from optimized BOM and the commercial viability regarding early investment requirements inherent in new development models merit careful evaluation.

When considering chiplets, OEMs have a few pathways to exploreThey can either rely heavily on their foundry and fabless partners to advance chiplet technology, actively participate in standardization bodies (e.g., UCIe), or take on the initiative to develop chiplets independently—though this route demands vast resources dedicated to forming specialized teams.

For tier-one suppliers, there exists a clear trajectory to follow the trend of fusion SoCs by leveraging the designs to construct centralized computing solutionsSuppliers can utilize these designs to communicate the potential technological and commercial benefits to OEMsSome tier-one suppliers have already embarked on this strategy, gearing up for production slated for 2026 to 2028.

Provided chip options may be comparable between tier-one suppliers and OEMs, there arises a compelling case for tier-one suppliers to begin discussions with OEMs early on, working to align their chip requirements with developers of the next generation of centralized computing units.

For foundries, IDMs, and fabless manufacturers, while the ascent and impact of fusion chips may be limited, the relevance of chiplet technology raises broader questions concerning the responsibilities and ownership of manufactured chips

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